1. Field of the Invention
The present invention relates to a semiconductor wafer, and more particularly, to a method of preventing micro-scratches on the surface of a semiconductor wafer during chemical mechanical polishing.
2. Description of the Prior Art
The CMP (chemical-mechanical polishing) process is a very commonly used semiconductor process. It is performed to planarize the surface of the semiconductor wafer by removing unwanted substance from it. The polish rate of the CMP process varies with the use of different polishing media and is therefore very difficult to control. This often leads to over-etching or under-etching. In a semiconductor wafer that has shallow trenchs, the CMP process is performed to remove only a portion of unwanted substance, and the remaining unwanted substance is removed by using a method with a more stable polish rate to prevent micro-scratches caused by over-etching.
Please refer to FIG. 1. FIG. 1 is a cross-sectional view of a prior art semiconductor wafer 10 before performing a CMP process. The semiconductor wafer 10 comprises a silicon substrate 12,a pad oxide layer 14 composed of silicon oxide (SiO.sub.x) formed on the silicon substrate 12, a second dielectric layer 16 composed of silicon nitride (Si.sub.3 N.sub.x) deposited on the pad oxide layer 14, a plurality of shallow trenches 18 positioned on the silicon substrate 12 for isolating components on the semiconductor wafer 10, and a first dielectric layer 20 composed of silicon oxide (SiO.sub.x) positioned on the second dielectric layer 16 for filling the shallow trenches 18.
Please refer to FIG. 2. FIG. 2 is a cross-sectional view of the semiconductor wafer 10 after performing the CMP process. When the CMP process is performed on the first dielectric layer 20 of the semiconductor wafer 10, a predetermined thickness of the first dielectric layer 20 is removed to make the surface of the semiconductor wafer 10 approximately even. Then the remaining height of the first dielectric layer 20 is measured. If the remaining thickness is within a predetermined range, the remaining first dielectric layer 20 is removed horizontally by performing an etching back process. Please refer to FIG. 3. FIG. 3 is a cross-sectional view of the semiconductor wafer 10 after performing the etching back process. After performing the etching back process, a flat surface is formed by the second dielectric layer 16 and several shallow trenches 18 on the semiconductor wafer 10.
Please refer to FIG. 4. FIG. 4 is a flowchart of a prior art etching method 22. To accurately perform the etching back process, the predetermined range of remaining thickness of the first dielectric layer 20 is defined very small. Because the polishing rate of the CMP process is unstable, the remaining thickness of the first dielectric layer 20 frequently exceeds the predetermined range. If the remaining thickness of the first dielectric layer 20 exceeds the predetermined range, the etching back process cannot be performed, and the operators have to stop the process and perform special, time-consuming manipulations. The etching method 22 is very rigid and often interrupts the process thus increasing the workload of process engineers.